There was a CMOVE architecture around 1990 (Israel), I think. It was very similar. Could not find it on internet, sadly.
The MOVE architectures may work best with digital signal processors, because the data-flow is almost constant in such processors.
I invented my own version of the move only architecture (around 1992), but focused on speed. So here is my idea below.
1. The CPU only moves within the CPU, like from one register to the other. So all moves are extremely fast.
2. The CPU is separated in different units that can do work separately. Each unit has different input and output ports. The ports and registers are connected via a bus.
3. The CPU can have more buses and thus do more moves at the same time. If an output-data is not ready, the instruction will wait.
Example instruction: OUT1 -> IN1, OUT2 -> IN2
With 32 bits it would give give 8 units with 32 ports each.
Example of some set of units and ports.
Control unit: (JUMP_to_address, CALL_to_address, RETURN_with_value, +conditionals)
Memory unit: (STORE_Address, STORE_Value, READ_Address, READ_Value),
Computation unit: (Start_Value, ADD_Value, SUB_Value, MUL_Value, DIV_Value, Result_Value)
Value unit: (Value_from_next_instruction, ZERO, ONE)
Register unit: (R0 ... R31)
It is extremely flexible. I also came up with a minimalist 8 bit version. One could even "plug-in" different units for different systems. Certain problems could be solved with adding special ports, which would work like a special instruction.
I did not continue the project due to people not understanding the bus architecture (like a PCI-bus). If you try to present it in a logical-gate architecture (like in the article), the units make the architecture more complicated than it actually is.
Of course, but you don't have the toy CPU under your desk or in your laptop running at several GHz nor are you likely to find it in a target that really needs a cute hack to obscure your exploit.
If you were interested in co-designing a CPU with software the TTA is an attractive way to do it, particularly in that it is easy to design it so you can do more than one MOV at the same time and thus have explicit parallelism.
The tough part though is that memory is usually slow and you have to wait an undetermined number of cycles for data to get back from DRAM and while one operation is blocked all the other operations are blocked.
I guess you could have something like this with a fancy memory controller that could be programming explicitly to start fetching ahead of time so data is available when it is needed, at least most of the time.
Just when my night was going through a meditative sleep about basing ontological models using change as fundamental block. Identity is such a brittle choice as foundation, even if it's a great tool in many situations otherwise.
Was it the Navajos whose language doesn't have nouns, only verbs? A noun is a kind of illusion of eternal identity. A chair is only chair-ing for the moment as a configuration of matter that was doing something else before, and will fall apart and transform into doing something else in the future.
IIRC Navajo has a pretty robust noun-verb distinction. However there definitely are other languages where nouns and verbs behave very similarly, e.g. most famously Salishan languages. That said, there don’t seem to be any natural languages in which nouns and verbs are completely indistinguishable — there’s always some minor difference in how they behave.
There was a CMOVE architecture around 1990 (Israel), I think. It was very similar. Could not find it on internet, sadly.
The MOVE architectures may work best with digital signal processors, because the data-flow is almost constant in such processors.
I invented my own version of the move only architecture (around 1992), but focused on speed. So here is my idea below.
1. The CPU only moves within the CPU, like from one register to the other. So all moves are extremely fast.
2. The CPU is separated in different units that can do work separately. Each unit has different input and output ports. The ports and registers are connected via a bus.
3. The CPU can have more buses and thus do more moves at the same time. If an output-data is not ready, the instruction will wait.
Example instruction: OUT1 -> IN1, OUT2 -> IN2 With 32 bits it would give give 8 units with 32 ports each.
Example of some set of units and ports. Control unit: (JUMP_to_address, CALL_to_address, RETURN_with_value, +conditionals) Memory unit: (STORE_Address, STORE_Value, READ_Address, READ_Value), Computation unit: (Start_Value, ADD_Value, SUB_Value, MUL_Value, DIV_Value, Result_Value) Value unit: (Value_from_next_instruction, ZERO, ONE) Register unit: (R0 ... R31)
It is extremely flexible. I also came up with a minimalist 8 bit version. One could even "plug-in" different units for different systems. Certain problems could be solved with adding special ports, which would work like a special instruction.
I did not continue the project due to people not understanding the bus architecture (like a PCI-bus). If you try to present it in a logical-gate architecture (like in the article), the units make the architecture more complicated than it actually is.
I've always loved quirky CPU designs like this, and having one layed out in logic gates is amazing.
I'm having trouble running the file though, it's missing a chip, "74181.dig". Can you point me to where to download that or add it to the repo?
[delayed]
The Intel architecture is already Turing complete when you just use MOV instructions: https://github.com/xoreaxeaxeax/movfuscator. Of course, you don't even need instructions at all: https://news.ycombinator.com/item?id=5261598
I came back to reply with just this. Christopher Domas's conference talk on the movfuscator is legendary:
https://www.youtube.com/watch?v=R7EEoWg6Ekk
While this is true, I suspect a spec compliant implementation of the x86 mov instruction would many use more transistors than OP’s entire CPU.
Of course, but you don't have the toy CPU under your desk or in your laptop running at several GHz nor are you likely to find it in a target that really needs a cute hack to obscure your exploit.
If you were interested in co-designing a CPU with software the TTA is an attractive way to do it, particularly in that it is easy to design it so you can do more than one MOV at the same time and thus have explicit parallelism.
The tough part though is that memory is usually slow and you have to wait an undetermined number of cycles for data to get back from DRAM and while one operation is blocked all the other operations are blocked.
I guess you could have something like this with a fancy memory controller that could be programming explicitly to start fetching ahead of time so data is available when it is needed, at least most of the time.
How would you handle context switching? You've got a whole lot of exposed state scattered throughout the whole CPU.
I played around making a TTA-ish thing as part of learning Verilog some years ago. It's a neat idea: https://github.com/rdaum/simple_tta
Looks like an interesting read, thank you @v9v.
Just when my night was going through a meditative sleep about basing ontological models using change as fundamental block. Identity is such a brittle choice as foundation, even if it's a great tool in many situations otherwise.
Many ancient cultures use behavior as identity. It certainly has a charm.
Was it the Navajos whose language doesn't have nouns, only verbs? A noun is a kind of illusion of eternal identity. A chair is only chair-ing for the moment as a configuration of matter that was doing something else before, and will fall apart and transform into doing something else in the future.
IIRC Navajo has a pretty robust noun-verb distinction. However there definitely are other languages where nouns and verbs behave very similarly, e.g. most famously Salishan languages. That said, there don’t seem to be any natural languages in which nouns and verbs are completely indistinguishable — there’s always some minor difference in how they behave.