I am devastated by this news. I was lucky enough to work with Mohamed and Andy for several projects (including taping out the world's first ChatGPT-authored silicon [0]), and I've never met people more passionate about making chip design and silicon tape-out accessible to all. This is a real loss for the academic and maker communities.
My understanding is that the TinyTapeout people were using efabless as a service provider and efabless was also providing some sponsorship, but that they are institutionally distinct. There's a LinkedIn post from the TinyTapeout folks that they're looking into alternatives.
That's a relief! And Tiny Tapeout has already done a beta with IHP's open-source 130nm BiCMOS SiGe PDK.
The IHP PDK is really a lot more exciting to me than the Skywater stuff because it's aimed at submillimeter analog things (450GHz fₜ, 650GHz fastest oscillator) and why would you fab a digital design in 130nm instead of just programming an FPGA?
Radiation tolerance is one case. For the price of a tiny tapeout run you could count on one hand how many qualified radiation tolerant ICs you could buy. There's some sauce involved with process choices for radiation tolerance, but one of critical things to do is use large features.
> why would you fab a digital design in 130nm instead of just programming an FPGA?
That’s an interesting concept. So an fpga implemented on a current 7nm process is more performant (clock speed and energy use) than an asic on a 130nm process? How about 40nm process? I feel like there’s a graph of intersecting lines here.
I think perf is usually relatively close between an optimized design in a 7 nm FPGA and an optimized design in ~40 nm CMOS, but it's not 1:1. The FPGAs are usually higher-performance than 130 nm, but there are certain things that are easier in ASICs (eg analog-related stuff).
Speaking as a newbie - FPGAs can't get anywhere near the same clock speed, though, right? So the equivalence only applies if the work is parallelizable?
The Sky130 IO pads can't go faster than 33Mhz (at least the ones in the open source PDK), and the OpenLane flow isn't yet timing driven, so anything internal isn't going to break more than 100Mhz. These aren't fast chips or fast processes, Skywater is mostly for pedagogical and niche military and research tapeouts.
With the exception of the highest clock speed chips (eg Intel CPUs), clock speeds can actually be comparable. 45 nm CPUs got to 2.5 GHz, and if you tickle a 7 nm FPGA just right it can get to ~800 MHz to a GHz. Things like microcontrollers and chips that are generally less optimized than the old Intel CPUs (which were mostly drawn at the transistor level and use a speed-optimized process) are much closer in speed. A 3-stage RISC-V at 45 nm is probably also running at 400 MHz or less, and the FPGA is capable of a 3 stage RISC-V at that speed.
But yes, in general, FPGAs on certain computational tasks will need deeper pipelines or the use of parallelism. Usually, pipeline depth works. Actually, if you look at the Intel front side bus (less optimized than the core), that's about the speed you can get from a 7 nm FPGA.
A few sq mm at 40 nm is about $20k, and you can only configure it once. I think the Versal also gives you more useful gates at that size (thanks to block RAMs and hard multipliers).
The FPGA will have higher static power (running all the overheads) but probably lower dynamic power for the same design. 40 nm is old at this point for high-performance chips.
You should really look into summaries on how deep sub-micron adds more problems as processes shrink. It's crazy that 28nm and under even work at all. They also break faster in more ways than larger, mature nodes.
Far as 130nm, I'll give you a few reasons I'd use one over a 7nm FPGA. This is a non-HW guy saying what he's heard from pro's at different times. HW people, feel free to correct me about whatever I get wrong.
1. Unit prices. If you can take the upfront cost (NRE), the per unit price will be much lower than FPGA's. You might charge plenty per unit depending on the market. This can be a source of profit.
2. Older, larger nodes are said to be better for analog. Lots of designs are mixed-signal to use analog for it's lower power, extra performance, or how it doesn't blink (no rise/fall with clock).
3. ASIC's can't be reprogrammed like FPGA's. The custom design might be more secure like Sandia Secure Processor (Score) or CHERI RISC-V. FPGA's can only do one of these except for antifuse FPGA's.
4. Larger nodes are easier to visually inspect for backdoor with cheaper, teardown hardware. Who knows what's in the FPGA's.
5. Larger nodes are easier to synthesize, P&R, and auto-inspect (eg Calibre). That means open-source tools have a better chance of working or even being developed.
6. If not too power hungry (or power is cheap), some applications can let you outperform 7nm parts with parallel use of 130nm parts which are much cheaper or highly-optimized. An example what media wanting to do distributed, massively-parallel design for doing NN training maybe with 8-bitters and on-board, analog accelerators. My inspiration, aside from old MPP clusters (eg Thinking Machines), was a wafer-scale, analog NN done before Cerebras.
7. Improved reliability in general. In trusted checkers or fault-tolerant configuration, I feel like the 130nm parts are less likely to have a double failure or fail before the 7nm nodes.
8. If there's a business case, saying you built your own hardware is cool. It might even attract talent who benefit the company in other ways.
That's off the top of my head. Again, I just read a lot of stuff on ASIC's.
On a side note, you might find eASIC's Nextreme's interesting. They're Structured ASIC's that work like FPGA's in that design gets put on something with pre-made blocks to save money. Except, instead of software programmed, some via or metal layers get customized for the routing. While that reduces NRE cost, doing the routing in hardware supposedly reduces unit prices and energy maybe with a performance boost. They used to sample chips out quickly and relatively cheaply. Also, I think Triad Semiconductor had S-ASIC's with analog stuff.
eASIC Nextreme sounds like a good ol' fashioned ULA (uncommitted logic array), the sort of thing that's at least as old as the Sinclair ZX81 (where it drove the per-unit cost through the floor).
I hadn't heard of that. Looking it up, it's a type of gate array which I believe inspired both S-ASIC's and devices like FPGA's. Here's an intro to each for those following along:
That put having chips made into the realm of possibilities for even a small business. Other costs might prevent that but I could see more stuff opening up. I also envisioned hard blocks done on those nodes for common components so the S-ASIC was used for custom logic (eg differentiators).
Thanks! Yeah, for analog the case is obvious, both because there's no such thing as an analog FPGA and because smaller feature size comes with big drawbacks for analog; that's why I said, "why would you fab a digital design in 130nm". The others I'm less sure about, but they do sound plausible.
Basically yes, but you have to generate the GDS-II from your Verilog yourself, you have to pay them several thousand dollars, the turnaround time is nearly a year, and your first and maybe second and third tapeout will probably have bugs that keep it from working at all.
There are open tool chains that will compile your design using the cells defined in the outreach programs fab specific standards. However, it will not necessarily function like your simulated hardware design.
Getting the hardware cell simulation working is not trivial, and Synopsys charges more per seat than most startups spend on labor in a year.
I haven't paid that much attention, but in my utopia, they would have received some funding from the CHIPS act just to act as a gateway for educating people on how to design and make chips. But we live here.
Carver Mead & Lynn Conway got countless students & interested parties out there, making chips. Introduction to VLSI Design was a book, but also a whole practice of getting out there and doing the thing for real. So so so much innovation & creativity followed.
Efabless felt like such a great hope that the tradition could continue, that maybe perhaps we could have a new age of newcomers also starting to make chips.
It’s still possible to get a chip made, via MPW, from SkyWater.
And you can still use all the open source stuff, like the eFabless pad frame, if you want. But you’ll have to work with SkyWater directly which does require various business agreements to be in place.
Muse semi is an easier path. For Europe there is Europractice which gives access to pretty much any technology.
The problem is access to software and fabs. EDA is expensive and nobody will give access to individuals. Same for fabs. They don't want to give access to a lot of people due to IP theft risks. Anyone can be a North Korean hacker. Plus they operate under US export controls which makes the paperwork daunting.
SkyWater's 130nm has been used for all (most?) of the Efabless × Google MPW (multi project wafer) runs. That PDK was open sourced as part of that initial effort.
Most PDKs have an NDA, but Skywater is an exception. Also, most PDKs have some software restrictions on their standard cells because they never tested them with the open-source tools, but with difficulty you can use their design rules in software like MAGIC.
MOSIS still exists, and Skywater has an MPW service that's easy to order from.
If you know the right person, TSMC also has an MPW service (as do most other foundries). Most of the slots on these services go toward high-volume customers and universities, especially at the high-tech PDKs.
Very sad to see Efabless go. They really did offer something unique with their chipIgnite programme. It provided a simple way to get a chip made at very low cost ($10k) with no barriers. Thanks to the open source toolchain and PDK you just needed your verilog and a credit card and you were good to go. Sure it had a bunch of limitations but it was still a very encouraging development in making chip design more accessible.
Other low-cost (at least low relative to the huge costs of silicon fabrication) services exist but typically they have little public information and will certainly require proprietary tools and PDKs (which are not cheap and require you to persuade the sales people to talk to you to even find out what these costs are).
Oof. I'm not totally surprised but this is such a shame. We talk about how we want to bring more of this industry back to the US and then this news drops. Our priorities still aren't right.
how much does a 130nm fab cost? I think 45 and 65 would be better, but ideally the fab could create 6502 and "486" CPUs as well, as those will always be in high demand.
It's ~$20k to get on an MPW, for 65 you can double that.
If you're talking about how much it takes to build the fab: infinity dollars, nobody builds new fabs in these nodes anymore. Skywater is barely keeping its head above water as-is and that's mostly wafer services, not tapeouts.
Focused ion beam milling and electron microscopy machine is under $5m, but your fab output volume for pre-doped CMOS epitaxial grown core-stack wafers would never offset the capital investment. This is a very real machine, and no I don't have one available at this time. Probably it is for the greater good. lol =3
There's something very hinky about this post. It links to efabless.com/notice, not efabless.com direcly, and there's no information about this on efabless.com proper. The title of the notice page is also "Website Title". Not to don my tinfoil hat prematurely, but might this be an attack on efabless's web hosting?
It's linked from the main website if you hit the "Log In" button and there was communication to customers about this, though I had the same initial reaction, which is why I looked around for corroboration before posting this.
This is what happens when you advertise a shuttle run for "open source" designs, brazenly backdoor everybody's chips with a Management Engine (google "eFabless Caravel") and then, to top it all off, act like you can just show up at CCC and pretend everything is fine:
Video from 38c3 talk 2024-Dec-29; question at time 31min:17sec.
This company, and its enablers (formerly) at Google, set back the progress of open source chip design by at least three full years with this bait-and-switch insanity. The people who could see through the ruse wouldn't touch it with a ten foot pole; meanwhile it sucked up all the students, momentum, and funding.
Think about what three years of progress is worth in the tech industry.
Caravel is fully open source. You can audit it. There is no ROM (except for a project ID), just 1.5KB of RAM, a CPU, a few peripherals and (most importantly) the pad ring.
Caravel is a (questionable) attempt to lower the barriers of entry to silicon design, both the cost and required skill.
It lowers cost, because every single chip on the MPW is the same size, and can be tested with a common interface. They can test the RISC-V core and pad ring to get a good indication of the die quality (theoretically they can upload user-submitted code to test the actual design, but I don't think have implemented that), and only package up the highest quality dies that are most likely to work.
It lowers required skill, because the user doesn't have to worry about getting the pad ring right. When they receive their chip, they are guaranteed to have a working RISC-V core, and caravel provides a bunch of logic analyser probes you can hook directly into your design to debug why it's not working.
It also meant anyone who actually wanted a CPU core in their design got something that was guaranteed to work and easy to integrate.
The Caravel harness makes it very clear what the target market for the eFabless product is. It's not for end products, you only get a few chips. It's for people, especially hobbyists to learn how to do silicon design. (Though, IMO it's nowhere near cheap enough for that target market.)
If you want an actual end product, you should be contracting either with eFabless or directly with Skywater for a full wafer with a custom pad ring.
My understanding is that there were problems with the whole Open PDK, and that most designs would have run into similar issues even if Caravel wasn't preventing IO configuration.
The didn't ship those early OpenMPW runs out at all, the designs where resubmitting to later runs. In a way, the incident proves the point: Caravel allowed them to quickly prove their yield for those early shuttles was essentially 0%, without needing to test the user design.
How would you do a multi-project chip without something like a "management engine"? By the nature of semiconductor fabrication, you have a bunch of identical chips, but you want each contributor to the chip to be able to use it for testing their own contribution. It seems like that means you need some way to dynamically configure which of the many projects on the chip are actually connected to its I/O pins?
To clarify, since unfortunately griefers are flagging your comment to impede the discussion, so I'm not allowed to reply to it: Tiny Tapeout is a multi-project chip, not a multi-project wafer (though it is one chip in a multi-project wafer). Typical minimum die sizes are 0.8mm², which is about 2 million potential transistors in 130nm processes. That's big enough to put many projects on a chip. That's why Tiny Tapeout cost US$300 while MPW prices start at about US$3000 and more typically US$9999+.
Yes, Tiny Tapeout has its own MUXing layer to select which user project should be connected.
The Caravel management engine is used for single project chips, but it is innocuous. It just allows debugging and probing signals, and use of common I/O structure for different user projects. You don't have to actively use it.
It's hardly hidden, too: you have to instantiate it.
Sidenote: On HN you can often get downvoted/flagged not only for what you say, but for the way you say it. I wouldn't really call it griefing, rather a call for more civil discussion. If an account is new or a throwaway it gets held to this standard even stronger because no one really wants to see a HN that's flooded by throwaway accounts writing Reddit style comments.
The comment in question said, "It's a multi-project wafer not a multi-project chip. They cut the wafer apart into individual chips. There is one project on each chip. This has been going on since the 1970s. It is a very well-understood process." There is absolutely nothing uncivil about that comment, and it clarified that we were talking about slightly different things, thus leading to a resolution of the apparent disagreement and, I think, broader perspective for both of us.
The only even slightly uncivil thing about it would be the implication that I didn't know what MPW was, but in fact that was entirely plausible and would have been an important lacuna to correct were it true.
It was an exemplary comment, and the people who flagged it so that I could not reply were being a pain in the ass for no reason.
All eFabless designs for the first two years of the program were multi-project wafers with single-project chips. And they still required the management engine.
Over the past year they tried an experimental "multi-project chip" (first samples shipped 14 months ago). But the management engine was a requirement long before this happened.
GP seems to have edited their comment, but I can't edit mine (even though it is only 8 minutes old)
Why do you need a management engine for that? Couldn’t you just bond the connections to the ones you want and leave the other disconnected? Basically just have all chips next to each other on the die and only use one?
That was a front door not a back door! They were 100% open about the fact that it was there and most people wanted it to be there. If it didn't exist they would have to invent it. Why should I be the slightest bit upset about this?
You shouldn't. It's an entirely sensible thing for them to have done. Integrating IO and test is a massive time sink, it's a chore. People don't spend much time on it and it easily goes wrong and the whole thing is toast. Mandating the use of a fixed block to solve all this, at the sacrifice of some flexibility is what the majority would want. I've been doing this 15 years, I have experience of taping out real-life products that need to work. I can only assume the person complaining has different experience.
interesting to try Grok an LLAMA instead of ChatGPT for AI generated chips not trying to compete to win jeopardy and politics. For simple digital designs the simulators are generally adequate and the bandwidth of the existing tinychips and test boards dont provide significant speed advantages. Good learning and teaching students, but not far enough along for practical product design and development. Also compare to deepseek?
I am devastated by this news. I was lucky enough to work with Mohamed and Andy for several projects (including taping out the world's first ChatGPT-authored silicon [0]), and I've never met people more passionate about making chip design and silicon tape-out accessible to all. This is a real loss for the academic and maker communities.
[0] https://cyber.nyu.edu/2024/07/22/chipchat-nyu-tandon-team-fa...
[flagged]
These were the Tiny Tapeout folks, right? Or am I confusing two different things? https://tinytapeout.com/ doesn't have any shutdown notices.
Looks like yes: https://store.efabless.com/products/tiny-tapeout-project
KenoFischer says no, Tiny Tapeout was using eFabless as their service provider and is looking into alternatives.
Something's fishy. https://efabless.com/news doesn't list any shutdown notices.
My understanding is that the TinyTapeout people were using efabless as a service provider and efabless was also providing some sponsorship, but that they are institutionally distinct. There's a LinkedIn post from the TinyTapeout folks that they're looking into alternatives.
That's a relief! And Tiny Tapeout has already done a beta with IHP's open-source 130nm BiCMOS SiGe PDK.
The IHP PDK is really a lot more exciting to me than the Skywater stuff because it's aimed at submillimeter analog things (450GHz fₜ, 650GHz fastest oscillator) and why would you fab a digital design in 130nm instead of just programming an FPGA?
Radiation tolerance is one case. For the price of a tiny tapeout run you could count on one hand how many qualified radiation tolerant ICs you could buy. There's some sauce involved with process choices for radiation tolerance, but one of critical things to do is use large features.
> why would you fab a digital design in 130nm instead of just programming an FPGA?
That’s an interesting concept. So an fpga implemented on a current 7nm process is more performant (clock speed and energy use) than an asic on a 130nm process? How about 40nm process? I feel like there’s a graph of intersecting lines here.
I think perf is usually relatively close between an optimized design in a 7 nm FPGA and an optimized design in ~40 nm CMOS, but it's not 1:1. The FPGAs are usually higher-performance than 130 nm, but there are certain things that are easier in ASICs (eg analog-related stuff).
Speaking as a newbie - FPGAs can't get anywhere near the same clock speed, though, right? So the equivalence only applies if the work is parallelizable?
The Sky130 IO pads can't go faster than 33Mhz (at least the ones in the open source PDK), and the OpenLane flow isn't yet timing driven, so anything internal isn't going to break more than 100Mhz. These aren't fast chips or fast processes, Skywater is mostly for pedagogical and niche military and research tapeouts.
With the exception of the highest clock speed chips (eg Intel CPUs), clock speeds can actually be comparable. 45 nm CPUs got to 2.5 GHz, and if you tickle a 7 nm FPGA just right it can get to ~800 MHz to a GHz. Things like microcontrollers and chips that are generally less optimized than the old Intel CPUs (which were mostly drawn at the transistor level and use a speed-optimized process) are much closer in speed. A 3-stage RISC-V at 45 nm is probably also running at 400 MHz or less, and the FPGA is capable of a 3 stage RISC-V at that speed.
But yes, in general, FPGAs on certain computational tasks will need deeper pipelines or the use of parallelism. Usually, pipeline depth works. Actually, if you look at the Intel front side bus (less optimized than the core), that's about the speed you can get from a 7 nm FPGA.
$4600 on ebay for a 7/10nm xilinx versal. So is 130nm/40nm ASIC cheaper than $4600?
A few sq mm at 40 nm is about $20k, and you can only configure it once. I think the Versal also gives you more useful gates at that size (thanks to block RAMs and hard multipliers).
What about power consumption?
The FPGA will have higher static power (running all the overheads) but probably lower dynamic power for the same design. 40 nm is old at this point for high-performance chips.
This is a single chip. At scale, the ASIC is absolutely cheaper.
https://www.digikey.de/en/product-highlight/e/efinix/titaniu...
Ok it's 14nm. Who cares.
> and why would you fab a digital design in 130nm instead of just programming an FPGA?
Because you need some analog features with your digital design.
IHP is excitinybut their PDK is horrible compared to major fabs like TSMC or GF. Anyone using it for products hate it.
You should really look into summaries on how deep sub-micron adds more problems as processes shrink. It's crazy that 28nm and under even work at all. They also break faster in more ways than larger, mature nodes.
Far as 130nm, I'll give you a few reasons I'd use one over a 7nm FPGA. This is a non-HW guy saying what he's heard from pro's at different times. HW people, feel free to correct me about whatever I get wrong.
1. Unit prices. If you can take the upfront cost (NRE), the per unit price will be much lower than FPGA's. You might charge plenty per unit depending on the market. This can be a source of profit.
2. Older, larger nodes are said to be better for analog. Lots of designs are mixed-signal to use analog for it's lower power, extra performance, or how it doesn't blink (no rise/fall with clock).
3. ASIC's can't be reprogrammed like FPGA's. The custom design might be more secure like Sandia Secure Processor (Score) or CHERI RISC-V. FPGA's can only do one of these except for antifuse FPGA's.
4. Larger nodes are easier to visually inspect for backdoor with cheaper, teardown hardware. Who knows what's in the FPGA's.
5. Larger nodes are easier to synthesize, P&R, and auto-inspect (eg Calibre). That means open-source tools have a better chance of working or even being developed.
6. If not too power hungry (or power is cheap), some applications can let you outperform 7nm parts with parallel use of 130nm parts which are much cheaper or highly-optimized. An example what media wanting to do distributed, massively-parallel design for doing NN training maybe with 8-bitters and on-board, analog accelerators. My inspiration, aside from old MPP clusters (eg Thinking Machines), was a wafer-scale, analog NN done before Cerebras.
7. Improved reliability in general. In trusted checkers or fault-tolerant configuration, I feel like the 130nm parts are less likely to have a double failure or fail before the 7nm nodes.
8. If there's a business case, saying you built your own hardware is cool. It might even attract talent who benefit the company in other ways.
That's off the top of my head. Again, I just read a lot of stuff on ASIC's.
On a side note, you might find eASIC's Nextreme's interesting. They're Structured ASIC's that work like FPGA's in that design gets put on something with pre-made blocks to save money. Except, instead of software programmed, some via or metal layers get customized for the routing. While that reduces NRE cost, doing the routing in hardware supposedly reduces unit prices and energy maybe with a performance boost. They used to sample chips out quickly and relatively cheaply. Also, I think Triad Semiconductor had S-ASIC's with analog stuff.
eASIC Nextreme sounds like a good ol' fashioned ULA (uncommitted logic array), the sort of thing that's at least as old as the Sinclair ZX81 (where it drove the per-unit cost through the floor).
I hadn't heard of that. Looking it up, it's a type of gate array which I believe inspired both S-ASIC's and devices like FPGA's. Here's an intro to each for those following along:
https://en.m.wikipedia.org/wiki/Gate_array
http://eda.ee.ucla.edu/EE201A-04Spring/ASICslides.ppt
I also found a link with the pricing of one. It was $45,000 for 45 prototypes on 45nm through eASIC.
https://www.design-reuse.com/news/25107/easic-45nm-asic-valu...
That put having chips made into the realm of possibilities for even a small business. Other costs might prevent that but I could see more stuff opening up. I also envisioned hard blocks done on those nodes for common components so the S-ASIC was used for custom logic (eg differentiators).
Thanks! Yeah, for analog the case is obvious, both because there's no such thing as an analog FPGA and because smaller feature size comes with big drawbacks for analog; that's why I said, "why would you fab a digital design in 130nm". The others I'm less sure about, but they do sound plausible.
One more gift for you, buddy.
https://en.m.wikipedia.org/wiki/Field-programmable_analog_ar...
https://www.anadigm.com/fpaa.asp
https://hasler.ece.gatech.edu/FPAA_IEEEXPlore_2020.pdf
wait, does 130nm imply i can send them verilog and receive ASICs in the mail?
Basically yes, but you have to generate the GDS-II from your Verilog yourself, you have to pay them several thousand dollars, the turnaround time is nearly a year, and your first and maybe second and third tapeout will probably have bugs that keep it from working at all.
There are open tool chains that will compile your design using the cells defined in the outreach programs fab specific standards. However, it will not necessarily function like your simulated hardware design.
Getting the hardware cell simulation working is not trivial, and Synopsys charges more per seat than most startups spend on labor in a year.
YMMV =3
That's a real shame.
I haven't paid that much attention, but in my utopia, they would have received some funding from the CHIPS act just to act as a gateway for educating people on how to design and make chips. But we live here.
We really need a silicon foundry model again, somewhere somehow, where folks can get experienced deigning chips.
America's such a technology hub because of our silicon foundry, because of MOSIS. https://en.wikipedia.org/wiki/MOSIS
Carver Mead & Lynn Conway got countless students & interested parties out there, making chips. Introduction to VLSI Design was a book, but also a whole practice of getting out there and doing the thing for real. So so so much innovation & creativity followed.
Efabless felt like such a great hope that the tradition could continue, that maybe perhaps we could have a new age of newcomers also starting to make chips.
It’s still possible to get a chip made, via MPW, from SkyWater.
And you can still use all the open source stuff, like the eFabless pad frame, if you want. But you’ll have to work with SkyWater directly which does require various business agreements to be in place.
See more here:
https://www.skywatertechnology.com/technology-and-design-ena...
Muse semi is an easier path. For Europe there is Europractice which gives access to pretty much any technology.
The problem is access to software and fabs. EDA is expensive and nobody will give access to individuals. Same for fabs. They don't want to give access to a lot of people due to IP theft risks. Anyone can be a North Korean hacker. Plus they operate under US export controls which makes the paperwork daunting.
> require various business agreements to be in place.
I assume they require an NDA for their PDK? Or can projects still be meaningfully open-source with the existing one?
SkyWater's 130nm has been used for all (most?) of the Efabless × Google MPW (multi project wafer) runs. That PDK was open sourced as part of that initial effort.
https://www.skywatertechnology.com/first-google-sponsored-mp...
https://github.com/google/skywater-pdk
There's a bunch of other PDKs running around now too. But progress does seem to have distinctly tapered off.
A bunch? I've only seen three—but that's still a huge improvement over zero pre-Skywater.
Most PDKs have an NDA, but Skywater is an exception. Also, most PDKs have some software restrictions on their standard cells because they never tested them with the open-source tools, but with difficulty you can use their design rules in software like MAGIC.
MOSIS still exists, and Skywater has an MPW service that's easy to order from.
If you know the right person, TSMC also has an MPW service (as do most other foundries). Most of the slots on these services go toward high-volume customers and universities, especially at the high-tech PDKs.
https://themosisservice.com/
RIP Lynn Conway. Huge loss to the industry. I hadn't realized she had passed until now.
China has one, apparently.
[dead]
Very sad to see Efabless go. They really did offer something unique with their chipIgnite programme. It provided a simple way to get a chip made at very low cost ($10k) with no barriers. Thanks to the open source toolchain and PDK you just needed your verilog and a credit card and you were good to go. Sure it had a bunch of limitations but it was still a very encouraging development in making chip design more accessible.
Other low-cost (at least low relative to the huge costs of silicon fabrication) services exist but typically they have little public information and will certainly require proprietary tools and PDKs (which are not cheap and require you to persuade the sales people to talk to you to even find out what these costs are).
Oof. I'm not totally surprised but this is such a shame. We talk about how we want to bring more of this industry back to the US and then this news drops. Our priorities still aren't right.
how much does a 130nm fab cost? I think 45 and 65 would be better, but ideally the fab could create 6502 and "486" CPUs as well, as those will always be in high demand.
It's ~$20k to get on an MPW, for 65 you can double that.
If you're talking about how much it takes to build the fab: infinity dollars, nobody builds new fabs in these nodes anymore. Skywater is barely keeping its head above water as-is and that's mostly wafer services, not tapeouts.
"3nm Chip Fab: $15-$20 Billion"
Not infinity, so time to start saving up... lol =3
TSMC, Samsung, or Intel might be able to build a 3nm fab for about that price (maybe it's more like $30 billion though).
You or I? No.
https://www.youtube.com/watch?v=GYcopzJ-T9w
Focused ion beam milling and electron microscopy machine is under $5m, but your fab output volume for pre-doped CMOS epitaxial grown core-stack wafers would never offset the capital investment. This is a very real machine, and no I don't have one available at this time. Probably it is for the greater good. lol =3
There's something very hinky about this post. It links to efabless.com/notice, not efabless.com direcly, and there's no information about this on efabless.com proper. The title of the notice page is also "Website Title". Not to don my tinfoil hat prematurely, but might this be an attack on efabless's web hosting?
It's linked from the main website if you hit the "Log In" button and there was communication to customers about this, though I had the same initial reaction, which is why I looked around for corroboration before posting this.
Ah thanks, that's what I was looking for.
Looks legit.
https://www.linkedin.com/posts/tinytapeout_were-very-sad-to-...
Totally expected. No business model at all. Miracle it worked for so many years.
The secret ingredient was probably government money.
This is what happens when you advertise a shuttle run for "open source" designs, brazenly backdoor everybody's chips with a Management Engine (google "eFabless Caravel") and then, to top it all off, act like you can just show up at CCC and pretend everything is fine:
https://media.ccc.de/v/38c3-the-design-decisions-behind-the-...
Video from 38c3 talk 2024-Dec-29; question at time 31min:17sec.
This company, and its enablers (formerly) at Google, set back the progress of open source chip design by at least three full years with this bait-and-switch insanity. The people who could see through the ruse wouldn't touch it with a ten foot pole; meanwhile it sucked up all the students, momentum, and funding.
Think about what three years of progress is worth in the tech industry.
It's not a backdoor.
Caravel is fully open source. You can audit it. There is no ROM (except for a project ID), just 1.5KB of RAM, a CPU, a few peripherals and (most importantly) the pad ring.
Caravel is a (questionable) attempt to lower the barriers of entry to silicon design, both the cost and required skill.
It lowers cost, because every single chip on the MPW is the same size, and can be tested with a common interface. They can test the RISC-V core and pad ring to get a good indication of the die quality (theoretically they can upload user-submitted code to test the actual design, but I don't think have implemented that), and only package up the highest quality dies that are most likely to work.
It lowers required skill, because the user doesn't have to worry about getting the pad ring right. When they receive their chip, they are guaranteed to have a working RISC-V core, and caravel provides a bunch of logic analyser probes you can hook directly into your design to debug why it's not working.
It also meant anyone who actually wanted a CPU core in their design got something that was guaranteed to work and easy to integrate.
The Caravel harness makes it very clear what the target market for the eFabless product is. It's not for end products, you only get a few chips. It's for people, especially hobbyists to learn how to do silicon design. (Though, IMO it's nowhere near cheap enough for that target market.)
If you want an actual end product, you should be contracting either with eFabless or directly with Skywater for a full wafer with a custom pad ring.
> It also meant anyone who actually wanted a CPU core in their design got something that was guaranteed to work and easy to integrate.
in theory only.
caravel had hold time violations and the pin configuration mostly didn’t work for the first 5 or 6 sponsored OpenMPW shuttles.
Yeah... guaranteed after the teething issues.
My understanding is that there were problems with the whole Open PDK, and that most designs would have run into similar issues even if Caravel wasn't preventing IO configuration.
The didn't ship those early OpenMPW runs out at all, the designs where resubmitting to later runs. In a way, the incident proves the point: Caravel allowed them to quickly prove their yield for those early shuttles was essentially 0%, without needing to test the user design.
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How would you do a multi-project chip without something like a "management engine"? By the nature of semiconductor fabrication, you have a bunch of identical chips, but you want each contributor to the chip to be able to use it for testing their own contribution. It seems like that means you need some way to dynamically configure which of the many projects on the chip are actually connected to its I/O pins?
To clarify, since unfortunately griefers are flagging your comment to impede the discussion, so I'm not allowed to reply to it: Tiny Tapeout is a multi-project chip, not a multi-project wafer (though it is one chip in a multi-project wafer). Typical minimum die sizes are 0.8mm², which is about 2 million potential transistors in 130nm processes. That's big enough to put many projects on a chip. That's why Tiny Tapeout cost US$300 while MPW prices start at about US$3000 and more typically US$9999+.
Yes, Tiny Tapeout has its own MUXing layer to select which user project should be connected.
The Caravel management engine is used for single project chips, but it is innocuous. It just allows debugging and probing signals, and use of common I/O structure for different user projects. You don't have to actively use it.
It's hardly hidden, too: you have to instantiate it.
Sidenote: On HN you can often get downvoted/flagged not only for what you say, but for the way you say it. I wouldn't really call it griefing, rather a call for more civil discussion. If an account is new or a throwaway it gets held to this standard even stronger because no one really wants to see a HN that's flooded by throwaway accounts writing Reddit style comments.
The comment in question said, "It's a multi-project wafer not a multi-project chip. They cut the wafer apart into individual chips. There is one project on each chip. This has been going on since the 1970s. It is a very well-understood process." There is absolutely nothing uncivil about that comment, and it clarified that we were talking about slightly different things, thus leading to a resolution of the apparent disagreement and, I think, broader perspective for both of us.
The only even slightly uncivil thing about it would be the implication that I didn't know what MPW was, but in fact that was entirely plausible and would have been an important lacuna to correct were it true.
It was an exemplary comment, and the people who flagged it so that I could not reply were being a pain in the ass for no reason.
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It's a multi-project wafer not a multi-project chip.
They cut the wafer apart into individual chips. There is one project on each chip.
This has been going on since the 1970s. It is a very well-understood process.
All eFabless designs for the first two years of the program were multi-project wafers with single-project chips. And they still required the management engine.
Over the past year they tried an experimental "multi-project chip" (first samples shipped 14 months ago). But the management engine was a requirement long before this happened.
GP seems to have edited their comment, but I can't edit mine (even though it is only 8 minutes old)
Tiny Tapeout is a multi-project chip not a multi-project wafer.
Why do you need a management engine for that? Couldn’t you just bond the connections to the ones you want and leave the other disconnected? Basically just have all chips next to each other on the die and only use one?
I/O pads (and their drivers) take up a huge amount of space. For some simpler ICs their die size is determined by their Pads.
That was a front door not a back door! They were 100% open about the fact that it was there and most people wanted it to be there. If it didn't exist they would have to invent it. Why should I be the slightest bit upset about this?
You shouldn't. It's an entirely sensible thing for them to have done. Integrating IO and test is a massive time sink, it's a chore. People don't spend much time on it and it easily goes wrong and the whole thing is toast. Mandating the use of a fixed block to solve all this, at the sacrifice of some flexibility is what the majority would want. I've been doing this 15 years, I have experience of taping out real-life products that need to work. I can only assume the person complaining has different experience.
interesting to try Grok an LLAMA instead of ChatGPT for AI generated chips not trying to compete to win jeopardy and politics. For simple digital designs the simulators are generally adequate and the bandwidth of the existing tinychips and test boards dont provide significant speed advantages. Good learning and teaching students, but not far enough along for practical product design and development. Also compare to deepseek?